1. Field Of The Invention
The present invention relates to packages for mounting and interconnecting semiconductor chips; more particularly, to packages for housing high speed, high power semiconductor chips in a three-dimensional array, for providing interconnections between the chips, and for dissipating the heat generated by the chips.
2. Description Of The Related Art
Many advances have been made in reducing the size of semiconductor devices, and thus in increasing the number of semiconductor devices on a chip. Accordingly, there has been an increase in the number of gates on each chip, in the number of leads (bonding pads) emanating from each chip, and in the electrical power consumed by and the heat generated by each chip. These increases in densities have required increases in the number of connections between chips, and thus larger overall packages. Dissipating the heat generated by semiconductor chips having large power handling capabilities has required larger packages. As used herein, the terms "chip", "semiconductor chip" and "semiconductor device" refer to a die having bonding pads provided thereon and which may be encapsulated in, for example, a plastic or ceramic materials with electrical interconnections between the bonding pads on the die and electrical contacts on the exterior of the capsule, and the terms "package," "microelectronic package," or "interconnect system" refer to devices for housing and/or interconnecting plural chips, semiconductor chips or semiconductor devices.
Two different types of packages have been used to provide connections between the various chips in a package, so-called "two-dimensional packages" and "three-dimensional packages." In a two-dimensional package semiconductor chips are provided on the exterior of the package and individual leads connecting the chips pass in the x, y and z directions within the package. Such a package usually comprises a plurality of wafers provided in a stack with x and y interconnects on the surface of or contained in the wafers and z direction interconnections passing through the wafers. In a three-dimensional package semiconductor chips are mounted within the package (semiconductor chips may also be provided on the exterior of a three-dimensional package) and leads passing in the x, y and z directions interconnect the various chips and provide electrical access to the chips. Accordingly, a three-dimensional package may incorporate a larger number of semiconductor chips, requiring a larger number of interconnections and greater cooling capabilities. Moreover, the interconnect system becomes more complicated because of the limited areas where x, y and z direction connections can be provided.
To determine the relative capabilities of different packages or interconnect systems several standards are utilized. The most common standard for comparing the relative capabilities of interconnect systems is the number of interconnects per unit volume of package. A similar standard is the number of pins (or leads) per unit volume of package. Other methods of comparison include computing the package volume per chip and the number of gates per unit volume of package.
Examples of three-dimensional packages are disclosed in U.S. Pat. No. 3,769,702 and U.S. Pat. No. 4,841,355, and an example of a two-dimensional package is illustrated in U.S. Pat. No. 3,705,332. Other U.S. patents pertaining to packages for semiconductor chips include the following: U.S. Pat. No. 3,775,844; U.S. Pat. No. 3,813,773; U.S. Pat. No. 3,917,983; U.S. Pat. No. 4,095,867; U.S. Pat. No. 4,268,956; and U.S. Pat. No. 4,283,754. The two and three-dimensional packages and interconnect systems illustrated in U.S. Pat. Nos. 3,705,332 and 3,769,702 utilize 50 mil. grids for the z-axis connections and have a pin density of approximately 940 pins per cubic inch Z-axis connections in two- and three-dimensional packages may be provided by "button interconnects," as disclosed in U.S. Pat. No. 3,541,222, U.S. Pat. No. 3,705,222, U.S. Pat. No. 3,775,844, and U.S. Pat. No. 4,268,956, all assigned to the assignee of the present invention.